It looks like they're only working with logic levels, rather than "actual" device simulation. It's reasonably common in the digital IC crowd to call this "transistor-level", but indeed, it's not what most EEs usually call a transistor-level simulation (where one would actually expect the behaviour to be modelled down to the behaviour of a transistor). If we insist on jargon, this is actually a switch-level simulation.
It looks like they're only working with logic levels, rather than "actual" device simulation. It's reasonably common in the digital IC crowd to call this "transistor-level", but indeed, it's not what most EEs usually call a transistor-level simulation (where one would actually expect the behaviour to be modelled down to the behaviour of a transistor). If we insist on jargon, this is actually a switch-level simulation.