It is my understanding that the ECC that you're talking about only protects data-in-flight between the module and whatever is reading or writing the data. It does not protect against corruption of data-at-rest, which is what is protected with ECC in DDR4 and older.
It's also my understanding that the DDR5 data-in-flight ECC is a mandatory feature because the link between the memory modules and everything else is so error-prone that the system would simply not function without it.
Taking a quick glace at the articles, I think it's the opposite, DDR5 protects data at rest only, because they want to make the chips so unreliable it can't work without it, not the bus.
But in practice, it will probably be more reliable than DDR4 without ECC, since now you need 2 cosmic ray flips, or 1 plus a manufacturing defect flip, and the defect flips will probably be uncommon-ish.
It's too bad data in flight isn't protected without old fashioned ECC on top of that, but it will probably be a big step up, the same way that flash memory is now very reliable even though the actual uncorrected errors are probably worse under the hood.
The problem with the DDR5 approach is there's no reporting mechanism, so while it will reduce the error rate of a marginal module, it doesn't let you know so you can replace it. In my experience with ECC modules, a module with some errors is a lot more likely to get more errors than one that's operating with zero errors.
But even without it, it would be no worse than DDR4 with no ECC at all, where the only indication of bad ram is just that it crashes or memtest fails.
It sounds like they intend to make the chips all slightly bad and then correct it, so a few errors here and there might not indicate a true bad stick that needs replacement anymore.
It's also my understanding that the DDR5 data-in-flight ECC is a mandatory feature because the link between the memory modules and everything else is so error-prone that the system would simply not function without it.