FPGA designer here. I don't think it's accurate to claim that SystemC is replacing VHDL and Verilog for ASIC/FPGA design. I view SystemC as a niche tool to allow software engineers to dabble in hardware design. I use C for embedded software, but would never dream of designing hardware in anything else except pure HDL. It's a bit like trying to write a letter in a foreign language using Google Translate-- the results are non-optimal and often comical.
While trying to learn HDL I felt like Verliog was more naturaly than VHDL. I didn't bother trying to learn SystemC or anything, organizing a project on Quartus or ISE is hard enough as it is with Verilog.
I need to go back to dabbling with my little Spartan3E board though.
