I agree with you, and wonder why it's so hard to make chips 3D, but have a quibble. Jack Kilby's integrated circuit wasn't planar. Gold wires connected each part. Jean Hoerni at Fairchild is the inventor of the fully planar process. http://aneeshpthankachan.blogspot.com/2014/01/era-of-integra...
to make a 2-D (1 layer) chip you need N mask/etch steps with probability P of failure, to make a slightly 3-D, 2 layer chip you need 2N steps and have a probability of P^2 of failure etc
Note that exponential term for probability of failure - 10000 layers means 10000N etch steps but P^10000 turns a 99.9% yield for 1 layer device into a .004% yield for a 3d 10k layer device .....
note: by 'layer' here I'm including all the metal/poly/passivization layers in a current device - also after each layer you'd have to leave space to plane the finished layer flat as a base for the next - which means insulation between them deep enough to fill in all the gaps in the previous layer plus vias - and as others mention some way to pull heat out of the core of what has historically been called a "hairy smoking golf-ball" CPU
If every step either worked perfectly or didn't work at all, that would be very convincing. But isn't the reality that defects are localized and that the rate of defects is more or less proportional to the amount of stuff you're making?
If you have a certain probability of failure in each transistor (I know, I know, ICs don't consist entirely of transistors, but let's simplify) then making more transistors by stacking layers needn't lead to more failures than making more transistors by making larger-area 2D chips.
Existing fabrication methods already produce some failures. In at least some cases, the way that's dealt with is to make the hardware able to cope with some bits not working, and then e.g. you can turn an 8-core chip with a defect in one core into a 6-core chip that you sell for less money, or a memory device with one block of memory not working into ... exactly the same as all your other devices because you already budgeted for a couple of blocks not working.
So I think the p^n issue is illusory: n doesn't get larger just because you're making your device in 3D, it gets larger because your device has more stuff in it, so the issue is large devices not 3D ones, and there are already known ways to deal with the fact that large devices often have defects. 3D devices might well have a higher failure rate per unit of stuff on them because the processes would be more complicated, because there are connections in more directions, because of thermal issues, etc., but that's a matter of increasing p, not of increasing n.
But isn't the reality that defects are localized and that the rate of defects is more or less proportional to the amount of stuff you're making?
Not all defects are local. Sometimes you have to throw out the entire wafer. The rate and kind of defects is specific to each step in the process and there are many steps.
To make a wafer of modern semiconductor devices is a process that takes up to 4 months! If you double the number of layers you're already looking at 8 months and without some improvement in the reliability of each step you definitely are squaring the probability of producing a defect free device.
Making a device with ten thousand layers would require completely different technology, since we can't wait 40,000 months for the chips to arrive.
Mostly people don't make fault tolerant hardware - instead we do die level tests (first on bare dies and then in depth on packaged ones) and toss the bad dies.
However we're talking here about building 3D stacked devices instead, to get speed we're going to build cubic CPUs (to reduce speed of light delays), not piles of single layer square CPUs, maybe 100 layers deep - certainly we can disable bad CPUs but that still means we're getting an error rate at P^100
